In recent years, demand has increased rapidly for solid-state image sensing devices used as image sensing devices for image input mainly in digital still cameras and video cameras.
For these types of solid-state image sensing devices, CCD and MOS-type image sensors are widely used. The former are widely used as high picture quality image sensing devices due to their higher sensitivity and lower noise than the latter. On the other hand, however, CCDs have high power consumption and high drive voltages, and moreover, cannot be produced through the ordinary semiconductor manufacture process and are therefore expensive. Furthermore, a problem with CCDs is that it is difficult to integrate the drive circuitry and other peripheral circuits. By contrast, MOS-type image sensors can make up for the above-described deficiencies.
As a typical MOS-type solid-state image sensing device, a CMOS solid-state image sensing device has been commercialized. A circuit diagram of one pixel of a CMOS solid-state image sensing device is shown in FIG. 11, with a plan view thereof shown in FIG. 12 and a cross-sectional view shown in FIG. 13.
In FIG. 11, reference numeral 1 indicates a photodiode (PD), 2 indicates a transfer MOS transistor that transfers a charge from the photodiode and 3 indicates a floating diffusion (FD) portion that temporarily stores the transferred charge. Reference numeral 4 indicates a reset MOS transistor for resetting the FD portion 3 and the PD 1, 5 indicates a selection MOS transistor for selecting a given line from the pixel array of the solid-state image sensing device. Reference numeral 6 indicates a source follower MOS transistor that converts the charge accumulated in the FD portion 3 into voltage and amplifies it with a source follower-type amplifier, 7 indicates an output line, shared by all pixels in a given column, that reads out a voltage signal of each pixel, and 8 indicates a constant current source for setting the output line 7 at a constant current.
Next, a brief description is given of the operation of the CMOS solid-state image sensing device shown in FIG. 11. Incoming light is converted into an electrical charge by the PD 1 and the converted charge is transferred to the FD portion 3 by the transfer MOS transistor 2 and stored. The FD portion 3 and the PD 1 are reset to a set voltage in advance by turning on the reset MOS transistor 4 and the transfer MOS transistor 2, and therefore the voltage at the FD portion 3 changes according to the charge generated by the incoming light. The voltage at the FD portion 3 is amplified by the source follower MOS transistor 6 and output to the output line 7. The relevant pixels are selected by turning the selection MOS transistor 5 ON. The light signal portion charge is measured by calculating, at a reading circuit, not shown, the difference between the FD portion 3 reset voltage and the voltage after light signal accumulation.
FIG. 12 shows an example of the layout of the pixel circuit shown in FIG. 11. Reference numeral 10 indicates the active region where the PD 1 is formed and 11 indicates the active region where the selection MOS transistor 5 and the source follower MOS transistor 6 are formed. Reference numeral 20 indicates the transfer MOS transistor 2 region, 21 indicates a region enclosed by a dashed line indicating the gate line of the transfer MOS transistor 2, and 30 indicates a portion formed by a semiconductor PN junction of the FD portion 3. Reference numeral 31 indicates a contact for drawing out an electrode from the diffusion region of the FD portion 3 and 32 is a metal electrode for drawing out the FD portion 3. Reference numeral 34 indicates polysilicon that will become both the FD portion 3 electrode as well as the MOS transistor 6 gate electrode, and 33 is a contact for forming a connection from the metal electrode 32 to the polysilicon electrode 34.
Reference numeral 40 indicates the reset MOS transistor 4 region and 41 indicates a contact for connecting the reset MOS transistor 4 to a reset power source. Reference numeral 50 indicates the gate region of the selection MOS transistor 5 and 51 indicates a contact for connecting to a VDD power source, 60 indicates the source follower MOS transistor 6 region, with the polysilicon electrode 34 electrically connected to the FD portion 3 as the gate electrode. Reference numeral 70 indicates a signal output line composed of first layer wiring and formed of metal electrodes, and 71 indicates a contact for connecting the signal output line 70 and the source electrode of an area 60 of the source follower MOS transistor 6.
A cross-sectional view along the line CC′ in the layout shown in FIG. 12 is shown in FIG. 13. Reference numeral 301 indicates an n-type silicon substrate, 302a indicates a p-type well, 302b indicates a p-type implantation layer, 303a indicates a transfer MOS transistor 2 gate oxidation film and 303b indicates a thin oxidation film on top of a light-receiving portion. Reference numeral 304 indicates the transfer MOS transistor 2 gate electrode, 305 indicates the PD 1 n-type cathode, and 306 indicates a surface p-type region for giving the PD 1 an implantation structure. Reference numeral 307a indicates a LOCOS oxidation film for element separation, 307b indicates a p-type channel stop layer, and 308 indicates a high-density n-type layer that forms the FD portion 3 and is also the transfer MOS transistor 2 drain region. In addition, reference numeral 309 indicates an interlayer insulation film that insulates the gate electrode 304 and the first metal layer 321 from each other, 320 indicates contact plugs, and 321 indicates the first metal layer which is an electrode for drawing out the FD portion 3. Reference numeral 322 indicates an interlayer insulation film that insulates the first metal layer 321 and a second metal layer 323 from each other, 323 indicates the second metal layer, 324 indicates an interlayer isolation film that insulates the second metal layer 323 and a third metal layer 325 from each other, 325 indicates the third metal layer, and 326 indicates a passivation film. In a color photoelectric conversion device, a color filter layer, not shown, and a microlens for improving sensitivity are further formed in a top layer of the passivation film 326.
Light incoming from the surface passes through an aperture without the third metal layer 325 and enters the PD 1. The light is absorbed by the PD 1 n-type cathode 305 or the p-type well 302a and electron-hole pairs are generated. The electrons are accumulated in the n-type cathode region.
However, with the conventional CMOS-type solid-state image sensing device described above, signal electrons generated in response to incoming light causes the output voltage to fluctuate. Of an electron-hole pair 330b generated beneath the transfer MOS transistor 2 gate electrode 304 in response to inclined incoming light 330a striking at an angle as shown in FIG. 13, the electron is attracted to the high-density n-type layer 308 that forms the FD portion 3 rather than the PD 1 n-type cathode 305.
Furthermore, light 331a striking the top of the transfer MOS transistor 2 gate electrode 304 is repeatedly reflected as shown in FIG. 13, and an electron-hole pair 331b is generated beneath the high-density n-type layer 308. The electron of this pair is attracted to the high-density n-type layer 308. If the first metal layer 321 is extended toward the aperture side to improve light shielding in order to prevent this from happening, the static capacitance of the FD portion 3 increases and the charge conversion coefficient decreases, resulting in deterioration of the S/N ratio.
Electrons that are captured directly by the FD portion 3 without passing through the PD 1 as described above become pseudo signals, increasing the noise of the solid-state image sensing device, reducing its dynamic range, increasing its dark signal, increasing its dark shading and so forth. Particularly when all the charges are transferred from the PD 1 to the FD portion 3 simultaneously and those charges are output in sequence to the signal line in a so-called electronic shutter operation, the longer the charges are held in the FD portion 3 the more the pseudo signals overlap, thereby causing phenomena known as shading and S/N ratio intraframe distribution to occur. For this reason, a way has long been sought of improving the light-shielding capability of conventional CMOS solid-state image sensing devices.
With CCD-type solid-state image sensing devices as well, usually a source follower-type amplifier circuit using floating diffusion is used on the final stage of the reading circuit. Japanese Patent Application Laid-Open No. 03-116840 shows an example using polysilicon for drawing of the electrode to the source follower amplifier. However, there is no mention of improving the light-shielding capability of the device in the invention described in Japanese Patent Application Laid-Open No. 03-116840, nor is there any consideration given to the flow of the electrons generated inside the silicon to the floating diffusion portion as shown in the conventional examples described above. Furthermore, with a CCD solid-state image sensing device, there is only one floating diffusion amplifier circuit in the later stage of a horizontal CCD, thus permitting to arrange the floating diffusion amplifier circuit far from the pixel portion and not restricted by the pixel surface area and thereby eliminating the need for additional engineering.
By contrast, with MOS-type solid-state image sensing devices there is a floating diffusion portion at every pixel, and thus the photodiode and the floating diffusion portions are close to each other. In addition, the metal electrode that functions as a light shield is also used as circuit wiring, and therefore a gap must be provided and the like. Therefore the situation is different from that of a CCD-type solid-state image sensing device, and requires more structural engineering.
A method for strengthening the light shielding of the floating diffusion portion in a MOS-type solid-state image sensing device is shown in Japanese Patent Application Laid-Open No. 2000-124438, and FIG. 14 is a diagram showing a cross-sectional view of the structure of the invention described therein. As shown in FIG. 14, a cylindrical light-shielding member 1009 is disposed atop the photodiode so as to cover the aperture portion.
However, although the structure described in Japanese Patent Application Laid-Open No. 2000-124438 can shield an area except for the aperture from light, it does so at the cost of performing the extremely difficult process of leaving the light-shielding member only at the side surfaces of fine pixels. Moreover, a latitudinal margin is also required to insulate the light-shielding member from a first layer wiring 1006 and a second layer wiring 1007. Consequently, the actual aperture is extremely narrow, which reduces sensitivity and is thus not a practical solution.